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Add multiple corners. #236

Merged
merged 1 commit into from
Nov 28, 2023
Merged

Add multiple corners. #236

merged 1 commit into from
Nov 28, 2023

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mithro
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@mithro mithro commented Nov 27, 2023

Add targets for fast, typical and slow corners (currently only support CCS model, but should be very easy to extend to NLDM in the future).

@mithro mithro requested a review from QuantamHD November 27, 2023 23:48
@mithro mithro force-pushed the asap7-multi-corner branch 5 times, most recently from d8576ff to 3690ccb Compare November 28, 2023 01:37
@mithro
Add multiple corners.
12dea9a 
Add targets for fast, typical and slow corners (currently only support
CCS model, but should be very easy to extend to NLDM in the future).

Signed-off-by: Tim Ansell <[email protected]>
@mithro mithro force-pushed the asap7-multi-corner branch from 3690ccb to 12dea9a Compare November 28, 2023 01:46
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mithro commented Nov 28, 2023 

tansell@tansell-top:~/github/hdl/bazel_rules_hdl$ bazel test //synthesis/tests/...
INFO: Invocation ID: 9dc856bd-46eb-4334-ad0d-f2905f871a6a
INFO: Analyzed 220 targets (0 packages loaded, 0 targets configured).
INFO: Found 150 targets and 70 test targets...
INFO: Elapsed time: 1.598s, Critical Path: 0.55s
INFO: 71 processes: 140 linux-sandbox.
INFO: Build completed successfully, 71 total actions
//synthesis/tests:build-verilog_counter                                  PASSED in 0.1s
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//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt_ccs_ff-gds PASSED in 0.1s
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//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_ff-synth PASSED in 0.1s
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//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_ss-gds PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_ss-place_and_route PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_ss-synth PASSED in 0.3s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_ss-synth_sta PASSED in 0.3s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_tt-gds PASSED in 0.3s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt_ccs_tt-place_and_route PASSED in 0.1s
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Executed 70 out of 70 tests: 70 tests pass.
tansell@tansell-top:~/github/hdl/bazel_rules_hdl$

@mithro mithro merged commit aca8d0a into hdl:main Nov 28, 2023
@mithro mithro deleted the asap7-multi-corner branch November 28, 2023 02:22
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@mithro @QuantamHD